The present invention relates generally to electronic design automation (EDA) of circuits and in particular to accelerating automatic test pattern generation (ATPG) in multi-core computing environments.
Scan compression technology is essentially logic that provides an interface between the scan-inputs/outputs and the internal scan chains. The architecture that is put into the design is based upon some user specified constraints that are related to the target compression and the available scan terminals. The configuration selected may or may not be the best suited for the design it is inserted in. Usually the architecture can be configured in many different ways. Some configurations are better suited for particular designs than others. If one were able to predict the configuration of the compression intellectual property (IP) to match the needs of the design then one would expect the best results from the compression technology.
As chip design sizes grow, large compute-intensive simulation operations like Test Compression/Coverage Maximization need to run longer for each individual run, and perform more runs due to increased parameter space exploration mandated by additional constraints from ATPG, Design-for-test (DFT), and other areas. Since the runtime is limited by test hardware, testing process has to speedup to limit the runtime of larger designs using existing current hardware capabilities. Maximizing test compression involves searching through the entire set of ATPG/DFT parameters (up to nine levels in the current implementation). The present method involves searching the parameter space in a breadth first fashion. In multi-core nodes, there is benefit in launching multiple sets parameter search runs in parallel. However, this can only be done on a per-level basis using current methods.